1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device and, particularly, to a method of manufacturing a semiconductor device having a plurality of gate insulating layers of different film thicknesses in one device.
2. Description of the Background Art
Among latest semiconductor devices, the number of those having gate oxide films of two or more film thicknesses (dual gate oxide) in one device has been increasing. A method of manufacturing a conventional semiconductor device having the dual gate oxide will be described in the following.
FIGS. 14 to 17 are schematic cross sections showing, in order, the steps of manufacturing the conventional semiconductor device having dual gate oxide. Referring to FIG. 14, a field oxide film 2 is formed on a surface of a silicon substrate 3, and thereafter, a first gate oxide film 1a is formed on silicon substrate 3 by thermal oxidation.
Referring to FIG. 15, a photoresist 105a is applied to be in direct contact with first gate oxide film 1a and field oxide film 2, and patterned by common photolithography. The gate oxide film 1a exposed through resist pattern 105a is removed, for example, by wet etching. Thereafter, resist pattern 105 is removed.
Referring to FIG. 16, at portions where the silicon oxide film has been removed by the wet etching, the surface of silicon substrate 3 is exposed. Thereafter, thermal oxidation is performed again.
Referring to FIG. 17, by the thermal oxidation, the second gate oxide film 1a is formed at the exposed surface of silicon substrate 3, and the thickness of the first gate oxide film 1a is increased. In this manner, thickness Ta of the first gate oxide film 1a is made thicker than the thickness Tb of the second gate oxide film 1b, and thus the dual gate oxide is completed.
In the process shown in FIGS. 14 to 17, however, photoresist 105a is formed to be in direct contact with first gate oxide film 1a as shown in FIG. 15. Generally, photoresist contains, as an impurity, Na (Sodium) or the like. Therefore, if photoresist 105a is formed to be in direct contact with gate oxide film 1a, Na in photoresist 105a enters gate oxide film 1a. Thus introduced Na undesirably provides conductivity to gate oxide film 1a or causes threshold voltage of MOS (Metal Oxide Semiconductor) transistor to deviate from the desired value, thereby significantly degrading reliability of the transistor.
For putting the wafer in a gate oxidation furnace to form second gate oxide film 1b, pre-processing such as processing with dilute hydrofluoric acid is performed. In the step of pre-processing, however, part of the first gate oxide film 1a is etched, and the thickness of the first gate oxide film 1a varies. Consequently, the threshold voltage of the MOS transistor deviates from the desired value, significantly degrading reliability of the transistor.
The following method has been proposed as a countermeasure.
FIGS. 18 to 23 are schematic cross sections showing, in order, the steps of manufacturing a conventional semiconductor device having the dual gate oxide which can solve the above described problem. Referring to FIG. 18, filed oxide film 2 is formed on silicon substrate 3, and thereafter, first gate oxide film 1a is formed by thermal oxidation. Thereafter, a first polycrystalline silicon film 204a doped with an impurity is formed on the entire surface, as a protective film for the first gate oxide film 1a.
Referring to FIG. 19, on the first polycrystalline silicon film 204a, a photoresist 205a is applied and patterned by common photolithography. The first polycrystalline silicon film 204a exposed from resist pattern 205a is removed by unisotropic etching. Thereafter, resist pattern 205a is removed.
Referring to FIG. 20, at portions where the first polycrystalline silicon film 204a has been removed, the first silicon oxide film 1a is exposed. In this state, the exposed first silicon oxide film 1a is removed by wet etching, and at that portion, the surface of silicon substrate 3 is exposed. Thereafter, thermal oxidation is performed again.
Referring to FIG. 21, by thermal oxidation, a second silicon oxide film 1b having film thickness different from that of the first silicon film 1a is formed on silicon substrate 3. Further, by the thermal oxidation, the surface of first polycrystalline silicon film 204a is also oxidized, and an oxide coating 6 of silicon oxide is formed. In this manner, the dual gate oxide having first and second silicon oxide films 1a and 1b of mutually different film thicknesses is formed.
Referring to FIG. 22, thereafter, a second polycrystalline silicon film 204b doped with an impurity is formed on the entire surface. A photoresist 205b is applied on the second polycrystalline silicon film 204b, and patterned by common photolithography. Using resist pattern 205b as a mask, the second polycrystalline silicon film 204 is unisotropically etched. Thereafter, resist pattern 205b is removed.
Referring to FIG. 23, by the unisotropic etching, the second polycrystalline silicon film 204b is patterned such that it is spaced from the first polycrystalline silicon film 204a. Thereafter, oxide coating 6 is removed, each of the first and second polycrystalline silicon films 204a and 204b is patterned, and a gate electrode layer is formed. By introducing an impurity using the gate electrode layer, field oxide film 2 and so on as a mask, a pair of source/drain regions (not shown) are formed at the surface of silicon substrate 3, on both sides of a lower region of gate electrode layer. Thus an MOS transistor is completed.
In the process shown in FIGS. 18 to 23, photoresist 205a is formed on the first polycrystalline silicon film 204a, as shown in FIG. 19, and not directly on the first gate oxide film 1a. Therefore, entrance of Na from photoresist 205a to the first gate oxide film 1a is prevented. Therefore, the first gate oxide film 1a is prevented from being rendered conductive, and variation of the threshold voltage of the MOS transistor is prevented.
At the time of processing of dilute hydrofluoric acid performed for putting the wafer into the gate oxidation furnace to form the second gate oxide film 1b, there is the polycrystalline silicon film 204a on the first gate oxide film 1a. Therefore, the first gate oxide film 1a is not etched in the process with diluted fluoric acid.
In the process shown in FIGS. 18 to 23, however, the second polycrystalline silicon film 204b is unisotropically etched as shown in FIGS. 22 and 23. The unisotropic etching leaves residue 204b.sub.1 of second polycrystalline silicon film 204b on a sidewall of the first polycrystalline silicon film 204a, in the form of a sidewall spacer. The residue 204b.sub.1 in the form of a sidewall spacer is so thin that it is readily separated or peeled off in the wet etching process for removing oxide coating 6, for example, possibly causing short-circuit between other conductive layers, and hence causing lower yield.